Copper is the preferred metal for creating multilevel interconnect structures in ultra-large-scale-integrated circuits because of its high electrical conductivity and electromigration resistance. One of the major challenges in Cu metallization technology is the prevention of the rapid diffusion of Cu into adjoining layers of SiO2 and related low-dielectric-constant materials (e.g., fluorinated SiOx, SiOCH) during device operation. This is because Cu incorporation into the dielectric degrades the dielectric properties of the insulating layer, causing increased leakage currents, and leading to inferior device performance and failure.
The current industry standard is 10-30-nm-thick metallic diffusion barrier layers of Ti- or Ta-based compounds (such as Ta, TaN, TiSiN and TiN) or Cu-based alloys to alleviate this problem. While these approaches have been successful thus far, barriers with thicknesses below 5 nm will be needed at sub-100-nm feature sizes and in advanced future device architectures (e.g. three-dimensional integrated multiple-wafer devices) to fully realize the advantage of Cu interconnects. It is difficult to obtain such thin barriers with acceptable step coverage by conventional metal deposition methods (Plasma Vapor deposition (PVD) or Chemical Vapor Deposition (CVD)) without compromising the barrier-layer microstructure and/or their conformality in high-aspect-ratio features. Additionally thick diffusion barrier layers take up the volume meant for low-resistivity Cu, reducing the advantages of scaling (miniaturization).
Newly emerging methods such as atomic layer deposition (ALD) have the potential to obviate some of these concerns. However, to obtain conformal films with thicknesses below 5 nm of conventional barrier materials, it is not clear if they will be effective due to high defectivity. Hence, there is a great deal of interest in exploring alternative materials and processing methods.
Recently, Self-Assembled Monolayers (SAM) are reported to act as thin (generally <2 nm) Cu diffusion barrier layers (US 2002/0079487). With SAM layers comprising organo-silane molecules, Cu diffusion into the dielectric is inhibited and a good Cu adhesion at the Cu/SiO2 interface is achieved. The use of said SAM layer in integrated circuit structures such as dual damascene structures wherein electrical contact is required between the metal line of interest to metal lines above or below the situation is more complicated. Deposition of said SAM layer (comprising organo-silane molecules) to the already existing metal structure will lead to poor adhesion of Cu seed layers prior to further Cu deposition and poor electrical conductivity later on in the finalized dual damascene structure.